Magnetic memory

ABSTRACT

A magnetic memory according to an embodiment includes: first to third terminals; a nonmagnetic conductive layer including first to third regions, the second region being disposed between the first and third regions, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first and second magnetic layers, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2017-178264, filed on Sep. 15, 2017, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to magnetic memories.

BACKGROUND

Recently, research and development of magnetic memories (magnetic random access memories (SOT-MRAMs)) that perform spin orbit torque (SOT) write operations has been actively performed. A memory element included in an SOT-MRAM has a structure in which magnetic tunnel junction (MTJ) elements each having a multilayer structure including a storage layer, a nonmagnetic layer, and a reference layer are disposed on a conductive nonmagnetic layers (also called “SO layers”). The magnetization direction of each storage layer is switched by causing a current to flow through the conductive nonmagnetic layer. A read operation is performed by causing a read current to flow between the conductive nonmagnetic layer and the reference layer through the storage layer and the nonmagnetic layer.

Magnetic memories that perform a write operation using spin transfer torque (STT) are also known (STT-MRAMs). A memory element of an STT-MRAM includes MTJ elements each having a multilayer structure including a storage layer, a nonmagnetic layer, and a reference layer. The magnetization direction of the storage layer is switched by causing a write current to flow between the storage layer and the reference layer via the nonmagnetic layer. A read operation is performed by causing a read current to flow between the storage layer and the reference layer via the nonmagnetic layer.

Since the read current path and the write current path are the same in the STT-MRAM, the element characteristics may vary if the device is miniaturized. Therefore, it is difficult to have enough margins among the read current, the write current, the current of the transistor connected to the MTJ element for selecting the MTJ element, and the breakdown current of the MTJ element by reducing the variations in the respective currents.

In the SOT-MRAM, the read current path is different from the write current path. Therefore margins to deal with the variations in the respective currents are relatively large. Thus, variations of the read current, the current of the transistor connected to the MTJ element for selecting the MTJ element, the breakdown current that may breaks the nonmagnetic layer of the MTJ element, the write current, and the electromigration current flowing through the SO layer may be allowed to some extent. The SOT-M RAM thus may have relatively broad margins to deal with variations in currents even if the memory elements are miniaturized (to improve the capacity of the memory). This is an advantage of the SOT-MRAM to the STT-MRAM.

However, the cell area of the SOT-MRAM including the memory elements is as large as 12 F², F being the minimum feature size, and the write efficiency (=Δ/Ic) of the SOT-MRAM is about 0.3, which is not so good. Thus, the SOT-MRAM is inferior in the cell area and the write efficiency to the STT-MRAM. These problems need to be solved.

An SOT-MRAM is known, which has a reduced cell area. The SOT-MRAM includes a memory cell in which a string of MTJ elements (memory elements) is disposed on an SO layer. The cell area of the SOT-MRAM with such a structure is reduced to 6.75 F² per one bit (one memory element), which enables to produce a large-capacity voltage-controlled magnetic memory. In order to employ this structure, however, a voltage assisted magnetic anisotropy control technique, which changes the magnetic anisotropy (coercive force) of the storage layer by applying a voltage to the MTJ element, is preferably used in the SOT write operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a photograph for explaining a problem of a memory cell included in an SOT-MRAM.

FIG. 2 is a graph showing the dependency of the spin Hall angle to the thickness of the conductive layer.

FIGS. 3A to 3C are a diagram showing the changes in SOT switching current density when the voltage anisotropy effect is used.

FIG. 4 is a perspective view of a memory cell included in a magnetic memory according to a first embodiment.

FIG. 5 is a cross-sectional view of a memory cell included in a magnetic memory according to a modification of the first embodiment.

FIG. 6 is a diagram showing the dependency of the write current density to the thickness of the Ir₉₀Ta₁₀ layer.

FIG. 7 is a perspective view of a memory cell included in a magnetic memory according to a second embodiment.

FIG. 8 is a cross-sectional view of a magnetic memory according to a modification of the second embodiment.

FIG. 9 is a diagram showing the result of measurements of switching current density Jc in the magnetic memory according to the modification of the second embodiment.

FIG. 10 is a perspective view of a memory cell included in a magnetic memory according to a third embodiment.

FIG. 11 is a diagram for explaining a write method of the magnetic memory according to the third embodiment.

FIG. 12 is a diagram for explaining the write method of the magnetic memory according to the third embodiment.

FIG. 13 is a diagram for explaining the effect of the magnetic memory according to the third embodiment.

FIG. 14 is a diagram for explaining the effect of a magnetic memory according to a modification of the third embodiment.

FIG. 15 is a perspective view of a magnetic memory according to a fourth embodiment.

DETAILED DESCRIPTION

How the present invention has been conceived is first described before embodiments of the present invention are described.

As described above, the SOT-MRAM is inferior in write efficiency to the STT-MRAM, and needs to improve the write efficiency. The write efficiency is defined by dividing thermal stability Δ (=E/kT) by average write current Ic (=Δ/Ic), where E is the height of energy barrier when the spin of the storage layer is parallel and antiparallel to the spin of the reference layer, Ic is an average value of the currents Ip and Tap ((Ia+Ip)/2) in a case where the spin of the storage layer is changed from a parallel state to an antiparallel state and a case where the spin is changed from an antiparallel state to a parallel state. The write efficiency of the SOT-MRAM needs to be improved.

FIG. 1 is a photograph of a cross-section around an MTJ element of a memory cell included in an SOT-MRAM that is actually fabricated, taken by a transmission electron microscope (TEM). The MTJ element included in the memory cell is disposed on a conductive layer (SO layer) of Ta having a thickness of 9.7 nm. As can be understood from FIG. 1, the surface of the conductive layer is oxidized in a region other than a region immediately below the MTJ element, where the conductive layer and an interlayer insulating film are in contact with each other, and the thickness of the region is reduced from 9.7 nm to 5.3 nm. The thickness of the oxidized portion of the layer thus is 4.4 (=9.7−5.3) nm.

FIG. 2 shows the result of measurements proving the dependency of the spin Hall angle θ_(SH) to the thickness of a conductive layer including a nonmagnetic heavy metal element. The conductive layer of the measurements shown in FIG. 2 includes β-Ta. The write current density Jc (=Ic/cross-sectional area of SO layer) is proportional to the absolute value of the spin Hall angle θ_(SH).

Jc=k·|θ _(SH)|

Where k denotes a proportional constant. Therefore, if the thickness t_(Ta) of the SO layer is reduced from 10 nm to 6 nm, for example, the average value of the write current I_(c) is reduced to 1/2.8. Thus, in order to reduce the write current, the thickness of the conductive layer may need to be reduced. However, as described above with reference to FIG. 1, if the thickness of the conductive layer is reduced to 6 nm, the thickness of the region in the conductive layer other than the region where the MTJ element is formed is reduced to 1.6 (=6−4.4) nm. This increases the resistance of the conductive layer, and the function as an electrode may be lost.

There is another problem. A voltage assisted magnetic anisotropy control technique is used for controlling an SOT-MRAM including a memory cell in which a string of MTJ elements is disposed on an SO layer. A characteristic of the voltage assisted magnetic anisotropy control technique is shown in FIGS. 3A to 3C. If a voltage of +1 V is applied to an MTJ element of the SOT-MRAM, the current density in the SO layer required to switch the magnetization of the storage layer of the MTJ element increases (FIGS. 3A and 3C), and if a voltage of −1 V is applied to the MTJ element, the current density in the SO layer required to switch the magnetization of the storage layer of the MTJ element decreases (FIGS. 3B and 3C). In this architecture of SOT-MRAM, the memory elements (MTJ elements) may be arranged with a high density, and a write operation may be simultaneously performed with a voltage of one pulse applied to the memory elements to switch the magnetization of the storage layer of the MTJ element. Therefore, the power consumption may be reduced. However, if a difference in write current density between a selected memory element and a non-selected memory element is smaller than variations in write current density among the memory elements, a write disturb error (WDE) may be caused. Although a voltage of ±1 V is applied to the MTJ element in the above description, the voltage of ±1 V is too much for an MTJ element having very thin films, and may cause a breakdown of the tunnel barrier. In other words, reliability of the MTJ becomes lower.

As described above, in order to reduce the write current, a material having a large spin Hall angle θ_(SH) is preferably used. Known examples of such a material are Ta, W, Re, Os, Ir, Pt, Au, Ag, alloys of these materials, and Cu—Bi. If a β-W film is formed in the noble gas Ar with oxygen (O₂), a maximum value at present θ_(SH)=−0.5 may be obtained (Nature Comm. DOI:10.1038/ncomms10644). According to a recent report, the spin Hall angle θ_(SH) of about 0.5 is obtained by Au_(0.9)Ta_(0.1) (Au with 10% of Ta) having a thickness of 10 nm (Intermag2017AM-01 by Spintec (Fert, Jaffres)).

The inventors of the present invention have studied hard to invent a magnetic memory with good write efficiency, which is obtained by using the voltage assisted magnetic anisotropy control technique. Embodiments of such a magnetic memory will be described below.

A magnetic memory according to an embodiment includes: a first terminal, a second terminal, and a third terminal; a nonmagnetic conductive layer including a first region, a second region, and a third region, the second region being disposed between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.

First Embodiment

A magnetic memory according to a first embodiment will be described with reference to FIG. 4. The magnetic memory according to the first embodiment is an SOT-MRAM including at least one memory cell. FIG. 4 shows such a memory cell 10. The memory cell 10 includes nonmagnetic conductive layers (SO layers) 12 a and 12 b, a magnetoresistive element (for example, an MTJ element) 20 disposed on the conductive layer 12 a, which serves as a memory element, a switching element 30, and a wiring line 40. The conductive layer 12 b is connected to the conductive layer 12 a. The conductive layer 12 a has a terminal (first terminal) 13 a, and the conductive layer 12 b has a terminal (second terminal) 13 b. The conductive layer 12 b may be eliminated. In such a case, the terminal 13 b is provided to the conductive layer 12 a, and the MTJ element 20 is disposed in a region of the conductive layer 12 a between the terminal 13 a and the terminal 13 b. The conductive layers 12 a and 12 b are conductive nonmagnetic layers, which generate a spin current when a current flows through them, to apply a spin obit torque (SOT) to a storage layer of the magnetoresistive element. Thus, the conductive layer 12 a is a conductive nonmagnetic layer having a spin orbit coupling function. Although a transistor is illustrated as the switching element 30 in FIG. 4, any switching element other than a transistor, which is turned on or off based on a control signal, may be used.

The magnetoresistive element 20 includes a storage layer (second magnetic layer) 21, in which the magnetization direction may be changed, a reference layer (first magnetic layer) 23, in which the magnetization direction is fixed, and a nonmagnetic layer (first nonmagnetic layer) 22 disposed between the storage layer 21 and the reference layer 23. The state “the magnetization direction may be changed” means that, after a write operation is performed, the magnetization direction may be changed, and the state “the magnetization direction is fixed” means that, after a write operation is performed, the magnetization direction is not changed. The storage layer 21 is connected to the conductive layer 12 a, and the reference layer 23 is connected to the wiring line 40. One (terminal) of the source and the drain of the transistor 30 is connected to the terminal 13 a of the conductive layer 12 a. The other (terminal) of the source and the drain and the gate (control terminal) of the transistor 30 are connected to a control circuit, which is not shown. The terminal 13 b of the conductive layer 12 b is grounded as shown in FIG. 4, or connected to the control circuit. The control circuit is also connected to the wiring line 40.

In this SOT-MRAM, a write operation is performed by causing, by means of the transistor 30, a write current I_(w) to flow through the conductive layers 12 a and 12 b between the terminal 13 a and the terminal 13 b, and a read operation is performed by causing, by means of the transistor 30, a read current I_(r) to flow through the terminal 13 a, the conductive layer 12 a, the magnetoresistive element 20, and the wiring line 40. Thus, the write current path and the read current path are different from each other.

When the write current I_(W) flows through the conductive layer 12 a in the write operation, spin-polarized electrons 14 a with one of up spin and down spin flow to the top surface side of the conductive layer 12 a and spin-polarized electrons 14 b with the other flow to the lower surface side of the conductive layer 12 a. This generates a spin current that applies a spin torque to the storage layer 21 of the magnetoresistive element 20 to switch the magnetization direction of the storage layer 21. Alternatively, a voltage may be applied, in the write operation, to the reference layer 23 of the magnetoresistive element 20 via a transistor that is not shown, as in a third embodiment that is described later. The applied voltage changes the uniaxial magnetic anisotropy of the storage layer 21 in the MTJ element 20 to enable the magnetization of the storage layer 21 to switch easily.

The conductive layers 12 a and 12 b of the magnetic memory according to the first embodiment include an alloy having a face-centered cubic (fcc) structure. The alloy is at least one selected from Ir—Ta, Ir—V, Au—V, Au—Nb, or Pt—V, or at least two of the above alloys selected and combined. As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including a single member. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c.” The alloy Ir—Ta, for example, means an alloy including Ir and Ta. The expression “IrTa” also means an alloy including Ir and Ta.

The material with the fcc structure improves the voltage assisted magnetic anisotropy control effect, and also the spin Hall angle of the conductive layer. Therefore, if such a material is used to form the conductive layer, and also the storage layer 21 (i.e., if both the conductive layer and the storage layer 21 are formed of a magnetic material having the same Δ), the switching current Ic may be reduced as compared to the case where another material is used for the conductive layer.

The reduction in switching current is observed for such materials as Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35). The materials Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35) preferably have the fcc structure.

As described above, the magnetic memory according to the first embodiment improves the write efficiency.

(Modification)

A modification of the magnetic memory according to the first embodiment will be described with reference to FIG. 5.

The magnetic memory according to the modification has the same structure as the magnetic memory according to the first embodiment shown in FIG. 4 except that the conductive layer 12 a has a multilayer structure including a conductive layer 12 a ₁ and a conductive layer 12 a ₂ (FIG. 5). The MTJ element 20 is disposed on the conductive layer 12 a ₁. Like the first embodiment, if the conductive layer 12 a ₁ includes Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35), the reduction in switching current is observed. The material may be one of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35), or two or more of these alloys that are combined.

A sample is prepared, in which an in-plane magnetization MTJ element 20 having a structure CoFeB (2 nm)/MgO (1.5 nm)/CoFeB (1.2 nm)/Co (0.6 nm)/Ru (0.9 nm)/CoFe (1.8 nm)/IrMn (8 nm)/Ta (5 nm) is disposed on the conductive layer 12 a having a two-layer structure including a Ta layer 12 a ₂ having a thickness of 5 nm and a Ir₉₀Ta₁₀ layer 12 a ₁ having a thickness of t nm. The storage layer 21 of the MTJ element 20 is the CoFeB layer having a thickness of 2 nm, the nonmagnetic insulating layer 22 is the MgO layer having a thickness of 1.5 nm, and the reference layer 23 has a multilayer structure including the CoFeB layer having a thickness of 1.2 nm, the Co layer having a thickness of 0.6 nm, the Ru layer having a thickness of 0.9 nm, and the CoFe layer having a thickness of 1.8 nm. The IrMn layer having a thickness of 8 nm is disposed on the reference layer 23, and the Ta layer having a thickness of 5 nm is disposed on the IrMn layer.

FIG. 6 shows the result of measurements of switching current density Jc relating to an SOT current for switching the magnetization of the storage layer 21 included in the MTJ element 20 of the sample, when the thickness t (nm) of the Ir₉₀Ta₁₀ layer 12 a ₁ is changed in a range from 1 nm to 12 nm. As can be understood from FIG. 6, the switching current density Jc decreases if the thickness t of the Ir₉₀Ta₁₀ layer is greater than 3 nm, and further decreases if the thickness is greater than 5 nm.

The decrease in the switching current can also be observed when the material of the conductive layer 12 a ₁ is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35). The tendency shown in FIG. 6 may also be observed when a material obtained by combining at least two of the above alloy is used for the conductive layer 12 a.

The magnetic memory according to the modification also decreases the write current and the power consumption. Furthermore, the magnetic memory according to the modification improves the write efficiency, like the first embodiment.

(Magnetic Material)

The magnetic materials of the storage layer 21 and the reference layer 23 in the first embodiment and its modification are not limited, but preferably at least one selected from Ni—Fe alloy, Co—Fe alloy, Co—Fe—Ni alloy, an amorphous material such as (Co, Fe)—(B), (Co, Fe, Ni)—(B), (Co, Fe, Ni)—(B)—(P, Al, Mo, Nb, Mn) or Co—(Zr, Hf, Nb, Ta, Ti), or a Heusler material such as Co—Fe—Al, Co—Fe—Si, Co—Mn—Si, or Co—Mn—Al. More preferably, the storage layer 21 and the reference layer 23 have a multilayer structure.

If the memory elements are densely disposed with intervals of 30 nm or less, the storage layer 21 preferably has a multilayer structure.

If the spin of the magnetic layer is parallel to the film plane (for example, the top surface of the multilayer structure), the multilayer structure preferably is CoFe(B)/nonmagnetic metal (one of Cu, Ag, and Au)/CoFe(B), Fe(CoB)/Cr/Fe(CoB), Mn-based Heusler alloy/MgO/Mn-based Heusler alloy, or fcc magnetic layer/nonmagnetic metal (Ru or Ir)/fcc magnetic layer/(Ta, W, Mo)/CoFeB. The expression CoFe(B) means that B (boron) may be included, therefore CoFeB or CoFe. Similarly, Fe(CoB) means Fe or FeCoB. The expression (Ta, W, Mo) means at least one of Ta, W, or Mo is included.

If the spin of the magnetic layer is perpendicular to the film plane, the multilayer structure preferably is Co(Fe)(B)/Pt/Co(Fe)(B), Co(Fe)(B)/Pd/Co(Fe)(B), Co(Fe)(B)/Ni/Co(Fe)(B), (Co/Pt)n/Ru, or Ir/(Co/Pt)m (with CoFeB disposed at the interface with the tunnel insulating layer), or fcc magnetic layer/nonmagnetic metal (Ru or Ir)/fcc magnetic layer/(Ta, W, Mo)/CoFeB.

The reference layer 23 preferably has one-directional magnetic anisotropy, and the storage layer 21 preferably has uniaxial magnetic anisotropy. The thickness of these layers is preferably from 0.1 nm to 10 nm. These magnetic layers need to be thick enough not to enter the superparamagnetic state, and therefore preferably have a thickness of 0.4 nm or more.

The magnetic characteristics of the aforementioned magnetic materials may be adjusted by adding thereto a nonmagnetic element such as silver (Ag), copper (Cu), gold (Au), aluminum (Al), magnesium (Mg), silicon (Si), bismuth (Bi), tantalum (Ta), boron (B), carbon (C), oxygen (O), nitrogen (N), palladium (Pd), platinum (Pt), zirconium (Zr), iridium (Ir), tungsten (W), molybdenum (Mo), or niobium (Nb). Other physical characteristics such as crystallinity, the mechanical characteristics, and the chemical characteristics may be adjusted by the addition of the nonmagnetic element.

The magnetic layer that is close to the tunnel insulating layer 22 in MTJ element 20 preferably includes a material having a large magnetic resistance (MR) such as Co—Fe, Co—Fe—Ni, or Fe-rich Ni—Fe, and the magnetic layer that is not in contact with the tunnel insulating layer preferably includes an amorphous material such as Ni-rich Ni—Fe, Ni-rich Ni—Fe—Co, or CoFeB to curb variations in switching current with the large MR being maintained.

The material of the reference layer 23 is not limited as long as the magnetization is stably fixed.

Specifically, the magnetization may be fixed in one direction if the magnetic layer has a three-layer structure such as Co(Co—Fe)/Ru (ruthenium)/Co(Co—Fe), Co(Co—Fe)/Rh (rhodium)/Co(Co—Fe), Co(Co—Fe)/Ir (iridium)/Co(Co—Fe), Co(Co—Fe)/Os (osmium)/Co(Co—Fe), Co(Co—Fe)/Re (rhenium)/Co(Co—Fe), amorphous material layer such as Co—Fe—B/Ru (ruthenium)/Co—Fe, amorphous material layer such as Co—Fe—B/Ir (iridium)/Co—Fe, amorphous material layer such as Co—Fe—B/Os(osmium)/Co—Fe, amorphous material layer such as Co—Fe—B/Re (rhenium)/Co—Fe, (Co/Pt)n/Ru/(Co/Pt)m/CoFeB (n and m each indicate the number of stacked layers), (Co/Pt) n/Ir/(Co/Pt)m/CoFeB, (Co/Pt)n/Re/(Co/Pt)m/CoFeB, or (Co/Pt)n/Rh/(Co/Pt)m/CoFeB. The expression (Co/Pt)n means that the two-layer structure Co/Pt is stacked n times, and (Co/Pt)m means that the two-layer structure Co/Pt is stacked m times.

An antiferromagnetic layer is preferably disposed near the multilayer structure. The antiferromagnetic layer may include Fe—Mn, Pt—Mn, Pt—Cr—Mn, Ni—Mn, Ir—Mn, NiO, or Fe₂O₃. With the aforementioned structure, the magnetization of the reference layer is stably fixed without being influenced by the current magnetic field from a bit line or a word line.

The stray field from the reference layer may be reduced (or adjusted) and the shift of the magnetization in the storage layer may be adjusted by changing the thickness of the two ferromagnetic layers included in the reference layer. The magnetic layer (the reference layer) need to be thick enough not to enter the superparamagnetic state, and therefore preferably have a thickness of 0.4 nm or more.

A nonmagnetic insulating material or a nonmagnetic metal is used to form the nonmagnetic layer 22 of the magnetoresistive element 20. The nonmagnetic insulating material is preferably an oxide such as AlOx, MgO, Mg—AlOx, or Mg—ZnOx. The composition does not need to be completely accurate from the stoichiometric point of view. For example, oxygen or nitrogen may further be added or removed. The nonmagnetic layer 22 is preferably as thin as possible to allow the tunneling current to flow. The nonmagnetic metal may be Cu, Ag, or Au.

Second Embodiment

A magnetic memory according to a second embodiment will be described with reference to FIG. 7. The magnetic memory according to the second embodiment includes at least one memory cell, which is shown in FIG. 7. The memory cell includes a conductive layer 12, terminals 13 a, 13 b ₁, and 13 b ₂, magnetoresistive elements 20 ₁ and 20 ₂, switches 25 ₁ and 25 ₂, and switches 30 ₁ and 30 ₂.

The conductive layer 12 includes the same material as the conductive layer 12 a of the first embodiment. The conductive layer 12 thus includes any of Ir—Ta, Ir—V, Au—V, Au—Nb, and Pt—V having the face-centered cubic (fcc) structure, or at least two of the above alloys that are combined to make an alloy. The conductive layer including such a material reduces the switching current Ic more than the conductive layer including a material other than the above materials, as in the case of the first embodiment. Like the first embodiment, the decrease in the switching current can be observed when the material of the conductive layer 12 is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35). The materials Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35) have the fcc structure.

The terminals 13 a, 13 b ₁, and 13 b ₂ are disposed on the lower surface of the conductive layer 12. In FIG. 7, the terminal 13 a is disposed between the terminal 13 b ₁ and the terminal 13 b ₂.

The magnetoresistive element 20 ₁ is disposed on the conductive layer 12 between the terminal 13 a and the terminal 13 b ₁, and the magnetoresistive element 20 ₂ is disposed on the conductive layer 12 between the terminal 13 a and the terminal 13 b ₂. The magnetoresistive element 20 _(i) (i=1, 2) includes a storage layer 21 disposed on the conductive layer 12, a nonmagnetic insulating layer 22 disposed on the storage layer 21, a reference layer 23 disposed on the nonmagnetic layer insulating layer 22, and a cap layer 24 disposed on the reference layer 23. The magnetization direction of the storage layer 21 included in the magnetoresistive element 20 ₁ and the magnetization direction of the storage layer 21 included in the magnetoresistive element element 20 ₂ are opposite to each other.

A switch 25 _(i) is connected to the cap layer 24 of the magnetoresistive element 20 _(i) (i=1, 2). A switch 30 ₁ is connected to the terminal 13 b ₁, and a switch 30 ₂ is connected to the terminal 13 b ₂.

In the magnetic memory having the above-described structure, a write operation is performed by applying a voltage to the cap layers 24 of the magnetoresistive elements 20 ₁ and 20 ₂ via the switches 25 ₁ and 25 ₂ to change the magnetic anisotropy of the storage layer 21 of each of the magnetoresistive elements 20 ₁ and 20 ₂, and then turning on the switches 30 ₁ an 30 ₂ to cause a write current I_(w) to flow from the terminal 13 a to the terminal 13 b ₁, and from the terminal 13 a to the terminal 13 b ₂. The direction of the write current flowing from the terminal 13 a to the terminal 13 b ₁ and the direction of the write current flowing from the terminal 13 a to the terminal 13 b ₂ are opposite to each other. Therefore, when a write operation is performed, the spin received by the storage layer of the magnetoresistive element 20 ₁ from the conductive layer 12 is opposite to the spin received by the storage layer of the magnetoresistive element 20 ₂ from the conductive layer 12. In a read operation, the switches 30 ₁ and 30 ₂ are turned off and the switches 25 ₁ and 25 ₂ are turned on, a read current is caused to flow from the terminal 13 a to the magnetoresistive element 20 ₁ and to the magnetoresistive element 20 ₂, and differential reading is performed by using outputs from the switches 25 ₁ and 25 ₂. A high-speed read operation can be performed in this manner.

The magnetic memory according to the second embodiment has a high-speed voltage control spintronic memory (VoCSM) architecture in which two magnetoresistive elements serve as one bit. The read operation of this memory is performed at a high speed by differentially reading data stored in the two magnetoresistive elements, and the write operation is performed with the magnetic anisotropy of the magnetoresistive element being reduced by a voltage effect to shorten the write time to 1/10 (to improve the write speed) as compared with a magnetic memory with the same write current density.

Generally, a memory of differential type requires a current, the amount of which is twice the normally used amount, since the directions of magnetization of the storage layers included in the two magnetoresistive elements need to be switch at a time. If an alloy such as Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35), or an alloy obtained by combining at least two of these alloys is used to form the conductive layer 12 of the second embodiment, the write current density may be considerably reduced, and thus a high-speed VoCSM architecture with low power consumption may be obtained.

The magnetic memory according to the second embodiment improves the write efficiency, like the magnetic memory according to the first embodiment.

(Modification)

A magnetic memory according to a modification of the second embodiment will be described with reference to FIG. 8. The magnetic memory according to the modification has a configuration in which the conductive layer 12 of the magnetic memory according to the second embodiment shown in FIG. 7 has a two-layer structure as in the modification of the first embodiment shown in FIG. 5. The conductive layer 12 thus has a multilayer structure including a conductive layer 12 ₁ and a conductive layer 12 ₂ as shown in FIG. 8. The magnetoresistive elements 20 ₁ and 20 ₂ are disposed on the conductive layer 12 ₁, and the terminals 13 a, 13 b ₁, and 13 b ₂ are connected to the conductive layer 12 ₂. The terminals 13 a, 13 b ₁, and 13 b ₂ may be connected to the conductive layer 12 ₁. As in the first embodiment, a decrease in write current is observed if the conductive layer 12 ₁ is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35). The material may be one of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35), or an alloy obtained by combining at least two of the above alloys.

A sample is prepared, in which the conductive layer 12 has a two-layer structure including a Ta layer 12 ₂ having a thickness of 5 nm, and a Au₉₀V₁₀ layer 12 ₁ having a thickness of t nm, and an in-plane magnetization MTJ element having a structure CoFeB (2 nm)/MgO (1.5 nm)/CoFeB (1.2 nm)/Co (0.6 nm)/Ru (0.9 nm)/CoFe (1.8 nm)/IrMn (8 nm)/Ta(5 nm) is disposed on the layer 12 ₁. The storage layer 21 is a CoFeB layer having a thickness of 2 nm, the nonmagnetic insulating layer 22 is a MgO layer having a thickness of 1.5 nm, and the reference layer 23 has a multilayer structure including a CoFeB layer having a thickness of 1.2 nm, a Co layer having a thickness of 0.6 nm, a Ru layer having a thickness of 0.9 nm, and a CoFe layer having a thickness of 1.8 nm. An IrMn layer having a thickness of 8 nm is disposed on the reference layer 23, and a Ta layer having a thickness of 5 nm is disposed on the IrMn layer.

FIG. 9 shows the result of measurements of switching current density Jc relating to an SOT current for switching the magnetization of the storage layer 21 included in the magnetoresistive element 20 of the sample, when the thickness t (nm) of the Au₉₀V₁₀ layer 12 ₁ is changed in a range from 1 nm to 12 nm. As can be understood from FIG. 9, the switching current density Jc decreases if the thickness t of the Au₉₀V₁₀ layer is greater than 3 nm, and further decreases if the thickness is greater than 5 nm.

The decrease in the switching current can also be observed when the material of the conductive layer 12 ₁ is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35). The tendency shown in FIG. 9 may also be observed when a material obtained by combining at least two of the above alloys is used for the conductive layer 12 ₁.

The magnetic memory according to the modification also decreases the write current and the power consumption. Furthermore, the magnetic memory according to the modification improves the write efficiency, like the second embodiment.

The magnetic material of the storage layer 21 and the reference layer 23 in the second embodiment and its modification is not limited, but preferably at least one selected from Ni—Fe alloy, Co—Fe alloy, Co—Fe—Ni alloy, an amorphous material such as (Co, Fe)—(B), (Co, Fe, Ni)—(B), (Co, Fe, Ni)—(B)—(P, Al, Mo, Nb, Mn) or Co—(Zr, Hf, Nb, Ta, Ti), or a Heusler material such as Co—Fe—Al, Co—Fe—Si, Co—Mn—Si, or Co—Mn—Al. More preferably, the storage layer 21 and the reference layer 23 have a multilayer structure.

If the memory elements are densely disposed with intervals of 30 nm or less, the storage layer 21 preferably has a multilayer structure.

If this multilayer structure is used for a magnetic memory according to a third embodiment, which is described below, the margin for preventing erroneous writing is increased by applying a voltage to magnetoresistive elements serving as a plurality of bits disposed on an SO layer, causing a current to flow through the SO layer, and switching the magnetization of only the storage layers of the magnetoresistive elements to which the voltage is applied. The margin can be further increased by changing the sign of voltage applied to the magnetoresistive elements, and switching the magnetization of the storage layers included in the magnetoresistive elements to which the negative voltage is applied. If the storage layers have a multilayer structure described above, the margin is increased further.

Third Embodiment

A magnetic memory according to the third embodiment is shown in FIG. 10. The magnetic memory according to the third embodiment is described with reference to FIGS. 10 to 12. The magnetic memory according to this embodiment includes at least one memory cell, the configuration of which is shown in FIG. 10.

The memory cell 10 includes a conductive layer 12, a plurality (for example eight) of magnetoresistive elements 20 ₁ to 20 ₈ disposed on one surface of the conductive layer 12 to be separate from one another, transistors 25 _(i) each corresponding to one of the magnetoresistive elements 20 _(i) (i=1, . . . , 8), transistors 30 and 31 for causing a current to flow through the conductive layer 12, and control circuits 110 and 120.

The material of the conductive layer 12 is any of Ir—Ta, Ir—V, Au—V, Au—Nb, and Pt—V having the face-centered cubic (fcc) structure, or an alloy obtained by combining at least two of these alloys. Like the first embodiment, the use of such a material to form the conductive layer may lead to a decrease in the switching current Ic as compared to the case where a material other than the above materials is used for the conductive layer.

Like the first embodiment, the decrease in the switching current can be observed if the material of the conductive layer is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35). Each of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35) has the fcc structure. The write current I_(w) flows through the conductive layer 12.

The direction of current flowing through the conductive layer 12 is controlled by the control circuit 110. When the current flows, electrons 14 a with up spin and electrons 14 b with down spin flow through the conductive layer 12. The directions of the spins of the electrons 14 a and 14 b are indicated by arrows.

Each magnetoresistive element 20 _(i) (1=1, . . . , 8) has a multilayer structure including a storage layer 21 disposed on the conductive layer 12, a nonmagnetic layer 22 disposed on the storage layer 21, and the reference layer 23 disposed on the nonmagnetic layer 22. The magnetoresistive element 20 _(i) (i=1, . . . , 8) may be either a magnetic tunnel junction (MTJ) element in which the nonmagnetic layer 22 is an insulating layer, or a giant magneto-resistive (GMR) element in which the nonmagnetic layer 22 is a nonmagnetic metal layer. If the magnetoresistive element is an MTJ element of in-plane magnetization type, in which the magnetization directions of the storage layer 21 and the reference layer 23 are parallel to the film plane, and perpendicular to the layer-stacking direction of the multilayer structure, a CoFeB layer, for example, is used as the storage layer 21, a MgO layer, for example, is used as the nonmagnetic layer 22, and a synthetic antiferromagnetic multilayer structure is used as the reference layer, which includes, for example, a CoFeB layer, a Ru layer disposed on the CoFeB layer, and a CoFe layer disposed on the Ru layer, the CoFeB layer and the CoFe layer being coupled by antiferromagnetic coupling via the Ru layer. In the in-plane magnetization MTJ element, an antiferromagnetic layer of IrMn, for example, is disposed on the reference layer 23 in order to fix the magnetization of the reference layer 23. Although the magnetoresistive elements 20 ₁ to 20 ₈ are disposed on the conductive layer 12 in FIG. 10, they may be disposed under the conductive layer 12.

The MTJ element is patterned to have a rectangular shape. The stable magnetization direction in the storage layer and the reference layer is along the long axes of these layers due to the shape magnetic anisotropy. The stable magnetization direction is indicated by arrows in FIG. 10. The stability is called “(long axis) uniaxial magnetic anisotropy.” The uniaxial magnetic anisotropy is dependent on the aspect ratio of the rectangle, the thickness of the storage layer, and the magnetization of the magnetic layer, and the write current threshold value I_(co), which is described later, is proportional to the uniaxial magnetic anisotropy. Each magnetoresistive element 20 _(i) (i=1, . . . , 8) is a 1-bit storage element, and the memory cell 10 is, for example, a 1-byte cell including 8 bits.

One (first terminal) of the source and the drain of each transistor 25 _(i) (i=1, . . . , 8) is electrically connected to the reference layer 23 of the corresponding magnetoresistive element 20 _(i), the other (second terminal) is connected to a selection line (not shown) for selecting the memory cell, and the gate (control terminal) is connected to a selection line (not shown) for selecting the corresponding magnetoresistive element 20 _(i). Therefore, each transistor 25 _(i) (i=1, . . . , 8) is also called a bit selection transistor for selecting the corresponding magnetoresistive element 20 _(i). Each magnetoresistive element 20 _(i) (i=1, . . . , 8) has a first terminal and a second terminal, the first terminal being connected to the conductive layer 12, and the second terminal being connected to the first terminal of the bit selection transistor 25 _(i). The gate (control terminal) and the second terminal of each of the bit selection transistors 25 ₁ to 25 ₈ is connected to the control circuit 120 so that the ON state and the OFF state of each bit selection transistor is controlled by the control circuit 120 and the potential applied to the second terminal of each of the magnetoresistive elements 20 ₁ to 20 ₈ is controlled.

One (first terminal) of the source and the drain of the transistor 30 is connected to the terminal 13 a, which is one of the two terminals 13 a and 13 b of the conductive layer 12, the other (second terminal) is connected to a power supply or a current source, and the gate (control terminal) receives a signal for selecting the memory cell 10. One (first terminal) of the source and the drain of the transistor 31 is connected to the terminal 13 b, which is the other of the two terminals 13 a and 13 b of the conductive layer 12, the other (second terminal) is connected to a power supply or a current source, and the gate (control terminal) receives a signal for selecting the memory cell 10. A write operation to write data to the storage layer 21 of each magnetoresistive element 20 _(i) (1=1, . . . , 8) is performed by causing a write current to flow between the transistors 30 and 31 through the conductive layer 12. The transistors 30 and 31 are also called “byte selection transistors.” The gate of each of the byte selection transistors 30 and 31 is connected to the control circuit 110 so that the ON state and the OFF state of the byte selection transistors 30 and 31 are controlled. The direction of the current flowing through the conductive layer 12 is also controlled by the control circuit 110. The transistor 31 may be eliminated, and the second terminal 13 b of the conductive layer 12 may be grounded.

In the following descriptions, each magnetoresistive element 20 _(i) (i=1, . . . , 8) is assumed to be an MTJ element. The nonmagnetic layer 22 of each MTJ element, which is a MgO layer for example, is thick enough (for example, about 2 nm) to restrict the tunneling current flowing through the nonmagnetic layer 22 to be 1 μA or less. Therefore, when the control circuit 120 turns on the bit selection transistor 25 _(i) (i=1, . . . , 8), a voltage of about 0.5 V may be applied to the storage layer 21.

When the voltage is applied to the storage layer of the MTJ element, perpendicular magnetic anisotropy is induced to provide a vertical component to the magnetization of the storage layer. As a result, the stability of the magnetization (uniaxial magnetic anisotropy) is weakened. Thus, when the bit selection transistor 25 _(i) (i=1, . . . , 8) is in the ON state, the write current threshold value I_(co) of the corresponding bit can be reduced. This state is called “bit half-selection state,” and the write current threshold value in this state is set to be I_(ch). In this embodiment, parameters of the layers such as the storage layer 21 are set so that the following formula, for example, holds:

I _(ch) ≈I _(co)/2  (1)

The conductive layer 12 includes a material having a large spin Hall effect or a large Rashba effect that provides the spin orbit coupling function. The conductive layer 12 is disposed under the MTJ element and electrically connecting adjacent MTJ elements in series. Typically, MTJ elements of 1 byte (eight) are connected in series. The thickness of the conductive layer 12 is generally about 10 nm, and the sheet resistance of the conductive layer 12 is as low as about 1000Ω. This allows the eight (1 byte) MTJ elements to be connected in series. The series resistance of the MTJ elements is about 10 kΩ, which is substantially the same as that of a minute transistor. Therefore, a required write current may be provided.

When the byte selection transistors 30 and 31 are turned on by the control circuit 110, a write current I_(w) flows through the conductive layer 12. In the memory cell 10 shown in FIG. 10, spin-polarized electrons with spin directed from the near side to the far side in the drawing are accumulated around the top surface of the conductive layer 12, and spin-polarized electrons 13 a, 13 b with spin directed from the far side to the near side in the drawing are accumulated near the lower surface of the conductive layer 12 due to the electron scattering caused by the spin orbit coupling in the conductive layer 12.

When a bit is selected in the memory cell 10 having the above-described configuration, data may be written to the bit due to the spin transfer torque caused by the accumulated spin-polarized electrons and the magnetization of the storage layer 21 when the write current I_(W) exceeds the threshold current I_(c0).

Similarly, when a bit is half-selected, data may be written to the bit due to the spin transfer torque caused by the accumulated spin-polarized electrons and the magnetization of the storage layer 21 when the write current I_(w) exceeds the threshold current I_(c0)/2.

(Write Method)

A method of writing data to the memory cell 10 shown in FIG. 10 will be described below with reference to FIGS. 11 and 12. In this embodiment, a two-stage write operation is performed on the memory cell 10. FIGS. 11 and 12 show a case where 1-byte data (0, 1, 1, 0, 0, 0, 0, 1) is written to the memory cell 10.

First, as shown in FIG. 11, the byte selection transistors 30 and 31 and the bit selection transistors 25 ₁ to 25 ₈ are turned on by means of the control circuit 110 and the control circuit 120, and a first potential (for example, a positive potential) is applied to the reference layers 23 of the MTJ elements 20 ₁ to 20 ₈, and a write current I_(w) is caused to flow between the first terminal 13 a and the second terminal 13 b of the conductive layer 12. At this time, the magnetization stability (uniaxial magnetic anisotropy) of the storage layers 21 in all of the MTJ elements 20 ₁ to 20 ₈ is weakened, and therefore the threshold current of the storage layers 21 is changed from I_(c0) to I_(ch), and data “0” is written to all of the MTJ elements 20 ₁ to 20 ₈, like (0, 0, 0, 0, 0, 0, 0, 0), by a write current I_(w0) (I_(w)>I_(w0)>I_(ch)). The write error rate may be reduced to about 10⁻¹¹ if the write current is about 1.5 times the threshold current. Therefore, the following formula holds:

I _(w0)≈1.5I _(ch)  (2)

Next, the bit selection transistors connected to bits to which “1” is to be written, for example the bit selection transistors 25 ₂, 25 ₃, and 25 ₈, are turned on by means of the control circuit 120, and a second potential (for example a negative potential) is applied to the reference layers 23 of the MTJ elements 20 ₂, 20 ₃, and 20 ₈. A positive potential is preferably applied to the other MTJ elements 20 ₁, 20 ₄, 20 ₅, 20 ₆, and 20 ₇ to reduce the error rate. The byte selection transistors 30 and 31 are also turned on by means of the control circuit 110 to cause a write current I_(w1) (I_(c0)>I_(w1)>I_(ch)) to flow through the conductive layer 12 in a direction opposite to the direction for writing the data “0.” As a result, data “1” is written to the storage layer 21 of each of the MTJ elements 20 ₂, 20 ₃, and 25 ₈ (FIG. 12). At this time, the formula holds, as in the aforementioned case:

I _(w1)≈1.5I _(ch)  (3)

Thus, 1-byte data (0, 1, 1, 0, 0, 0, 0, 1) can be written by the two-stage write operation. The two-stage write operation is made possible by the cooperation of the control circuit 110 and the control circuit 120. A first write circuit used in the first-stage write operation and a second write circuit used in the second-stage write operation in the two-stage write operation are connected to the control circuit 110 and the control circuit 120.

A read operation is performed in the following manner. When data is read from the memory cell 10, the byte selection transistors 30 and 31 and the bit selection transistors 25 ₁ to 25 ₈ of the memory cell 10 are turned on to select bits from which data is read. The resistance of each of the selected bits is measured using a current flowing between the selection transistor connected to the selected bit and one of the byte selection transistors, and type of data is determined based on the measured resistance.

In the foregoing and the following embodiments, MTJ elements with in-plane magnetization are described. However, the magnetoresistive elements are not limited to this type, but MTJ elements with perpendicular magnetization, for example, may also be used. As in the case of the MTJ elements with in-plane magnetization, the bit selection transistors are turned on, and bits are selected by decreasing or increasing the write threshold current.

As described above, in the memory cell according to the third embodiment, an alloy having the face-centered cubic (fcc) structure such as Ir—Ta, Ir—V, Au—V, Au—Nb, or Pt—V, or an alloy obtained by two or more of the above alloys is used as the material of the conductive layer 12. By using such a material to form the conductive layer, the switching current Ic may be decreased as compared to the case where a material other than the above-described materials are used to form the conductive layer, as in the case of the first embodiment.

FIG. 13 shows a result of measurements of the current density Jsw, at which the magnetization of the storage layer is switched, when a write operation is performed by applying a voltage to the reference layer of one of the magnetoresistive elements included in the memory cell 10 according to the third embodiment (VoCSM), and when a write operation is performed only by causing a current to flow through the conductive layer 12 without applying a voltage to the MTJ element. As can be understood from FIG. 13, the write speed in the case where the magnetic anisotropy of the magnetoresistive element is reduced by the voltage (VoCSM) is higher than the write speed in the write operation using the spin Hall effect, when the write current density is the same.

A voltage may be applied to the reference layer of the magnetoresistive element also in the first embodiment, the second embodiment, and their modifications.

The magnetic memory according to the third embodiment improves the write efficiency, like the magnetic memory according to the first embodiment.

(Modification)

A magnetic memory according to a modification of the third embodiment will be described below. The magnetic memory according to the modification has a structure in which the conductive layer 12 of the magnetic memory according to the third embodiment shown in FIG. 10 has two layers, like the modification of the first embodiment shown in FIG. 5. The conductive layer 12 has a multilayer structure including a first conductive layer and a second conductive layer, and the magnetoresistive elements 20 ₁ to 20 ₈ are disposed on the first conductive layer. The material of the first conductive layer is the same as the conductive layer 12, i.e., any of Ir—Ta, Ir—V, Au—V, Au—Nb or Pt—V having the fcc structure, or an alloy obtained by combining at least two of the above alloys. The material of the second conductive layer is a well-known SO-layer material such as Ta or W.

In the modification, the conductive layer 12 has a two-layer structure including a Ta layer having a thickness of 5 nm and a Pt₉₀V₁₀ layer having a thickness of t nm. An MTJ element with in-plane magnetization is formed on the conductive layer, the MTJ element having a multilayer structure expressed as CoFeB (2 nm)/MgO (1.5 nm)/CoFeB (1.2 nm)/Co (0.6 nm)/Ru (0.9 nm)/CoFe (1.2 nm)/IrMn (8 nm)/Ta (5 nm). Thus, the MTJ element has a multilayer structure including a CoFeB layer having a thickness of 2 nm, an MgO layer having a thickness of 1.5 nm, a CoFeB layer having a thickness of 1.2 nm, a Co layer having a thickness of 0.6 nm, a Ru layer having a thickness of 0.9 nm, a CoFe layer having a thickness of 1.8 nm, a IrMn layer having a thickness of 8 nm, and a Ta layer having a thickness of 5 nm, the layers being stacked in this order. A sample is prepared, in which an MTJ element with perpendicular magnetization having a multilayer structure expressed as (Co (0.4 nm)/Pt (0.4 nm))n/CoFeB (1.0 nm)/MgO (1.5 nm)/CoFeB (1.0 nm)/Ta (0.5 nm)/(Co (0.4 nm)/Pt (0.6 nm))m/Ir (0.5 nm)/(Co (0.4 nm)/Pt (0.6 nm))k is formed on the same conductive layer. FIG. 14 shows a result of measurements of the switching current density Jc relating to the SOT current for the MTJ elements with in-plane magnetization and the MTJ element with perpendicular magnetization when the thickness t of the Pt₉₀V₁₀ layer in the conductive layer is changed to 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, and nm. In the measurements of the MTJ element with perpendicular magnetization, an in-plane magnetic field H_(ex)=100 Oe is applied to perform the switching by using the SOT.

A voltage of 1 V is applied to the MTJ elements of both types in order to reduce the switching current by the voltage controlled magnetic anisotropy effect. As can be understood from FIG. 14, the switching current Jc decreases when the thickness t is 3 nm or more, more preferably 5 nm or more.

The decrease in the switching current is also observed when the material of the first conductive layer is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35). A material obtained by combining at least two of the above alloys may also be used to form the first conductive layer to have a similar effect to FIG. 14.

The magnetic memory according to the modification reduces the write current and the power consumption. Furthermore, the magnetic memory according to the modification improves the write efficiency, like the magnetic memory according to the third embodiment.

Fourth Embodiment

A magnetic memory according to a fourth embodiment will be described below with reference to FIG. 15. As shown in FIG. 15, the magnetic memory according to the fourth embodiment includes memory cells 10 ₀₀, 10 ₀₁, 10 ₁₀, and 10 ₁₁, word lines WL₀₀ and WL₁₀, bit lines BL₀₀ to BL₇₀ and BL₀₁ to BL₇₁, write bit lines WBL₀ and WBL₁, and source lines SL₀ and SL₁.

Each memory cell 10 _(ij) (i, j=0, 1) includes a nonmagnetic conductive layer 12, memory elements (magnetoresistive elements) 20 ₀ to 20 ₇ disposed on the conductive layer 12, selection transistors 25 ₀ to 25 ₇, and a selection transistor 30. Each conductive layer 12 has a first terminal 13 a and a second terminal 13 b. Like the magnetic memory 10 according to the first embodiment shown in FIG. 4, each memory element 20 _(j) (j=0 . . . , 7) has a multilayer structure including a storage layer 21, a nonmagnetic layer 22, and a reference layer 23.

The magnetic memory according to the fourth embodiment has first to fourth levels 400, 410, 420, and 430.

In the first level 400, the selection transistors 25 ₀ to 25 ₇ and the selection transistor 30 of each memory cell 10 _(ij) (i, j=0, 1), the word lines WL₀₀ and WL₁₀, the write bit lines WBL₀ and WBL₁, and the bit lines BL₀₀ to BL₇₁ are disposed.

In the second level 410, vias and wiring lines connecting to the first level 400, and the memory elements 20 ₀ to 20 ₇ and the conductive layer 12 of each memory cell 10 _(0j) (j=0, 1) are disposed. The solid line 411 indicates a region including the memory elements 20 ₀ to 20 ₇ and the conductive layers 12 of the memory cells 10 ₀₀ and 10 ₀₁.

In the third level 420, vias and wiring lines connecting to the second level 410 and the fourth level 430 and source lines SL₀ and SL₁ are disposed.

In the fourth level 430, vias and wiring lines connecting to the third level 420, and the memory elements 20 ₀ to 20 ₇ and the conductive layer 12 of each the memory cell 10 _(1j) (j=0, 1) are disposed. The solid line 431 indicates a region including the memory elements 20 ₀ to 20 ₇ and the conductive layers 12 of the memory cells 10 ₁₀ and 10 ₁₁.

The selection transistors 25 ₀ to 25 ₇, the selection transistors 30, the word lines WL₀₀ and WL₁₀, the bit lines BL₀₀ to BL₇₀ and BL₀₁ to BL₇₁, and the write bit lines WBL₀ and WBL₁ are disposed in the first level 400.

The memory cells 10 ₀₀ and 10 ₀₁ are disposed in the second level 410. The source lines SL₀ and SL₁ are disposed in the third level 420. The memory cells 10 ₁₀ and 10 ₁₁ are disposed in the fourth level 430.

In each of the memory cells 10 ₀₀ and 10 ₁₀, the reference layer of the memory element 20 _(j) (j=0, . . . , 7) is connected to one of the source and the drain of the selection transistor 25 _(j), and the other of the source and the drain of the selection transistor 25 _(j) is connected to the bit line BL_(j0).

In each of the memory cells 10 ₀₁ and 10 ₁₁, the reference layer of the memory element 20 _(j) (j=0, . . . , 7) is connected to one of the source and the drain of the selection transistor 25 _(j), and the other of the source and the drain of the selection transistor 25 _(j) is connected to the bit line BL_(j1).

In each of the memory cells 10 ₀₀ and 10 ₁₀, the first terminal 13 a is connected to one of the source and the drain of the selection transistor 30, and the other of the source and the drain of the selection transistor 30 is connected to the write bit line WBL₀. The second terminal 13 b is connected to the source line SL₀.

In each of the memory cells 10 ₀₁ and 10 ₁₁, the first terminal 13 a is connected to one of the source and the drain of the selection transistor 30, and the other of the source and the drain of the selection transistor 30 is connected to the write bit line WBL₁. The second terminal 13 b is connected to the source line SL₁.

The write operation and the read operation performed on each memory cell 10 _(ij) (i, j=0, 1) of the fourth embodiment having the above-described configuration are the same as those for the magnetic memory according to the third embodiment.

The material of each conductive layer 12 of the fourth embodiment is any of Ir—Ta, Ir—V, Au—V, Au—Nb, and Pt—V having the face-centered cubic (fcc) structure, or an alloy obtained by combining at least two of the above alloys. The conductive layer formed of any of the above-described materials may reduce the switching current Ic as compared to the conductive layer formed of a material other than the above-described materials, when the material of the storage layer 21 is the same (has the same Δ).

The reduction in the switching current may also be observed when the material is any of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35). Each of the materials Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35) has the fcc structure.

As described above, the magnetic memory according to the fourth embodiment can improve the write efficiency, like the magnetic memory according to the third embodiment.

(Modification)

A magnetic memory according to a modification of the fourth embodiment has a configuration in which each of the conductive layers 12 in the magnetic memory according to the fourth embodiment has a multilayer structure including a first conductive layer and a second conductive layer, and the magnetoresistive elements 20 ₀ to 20 ₇ are disposed on the first conductive layer, like the modification of the third embodiment. The material of the first conductive layer is the same as that of the conductive layer 12, i.e., any of Ir—Ta, Ir—V, Au—V, Au—Nb, and Pt—V having the fcc structure, or an alloy obtained by combining at least two of the above alloys. The material of the second conductive layer is a well-known SO-layer material such as Ta or W.

The magnetic memory according to the modification improves the write efficiency, like the magnetic memory according to the fourth embodiment.

If the magnetoresistive elements are MTJ elements in the first to fourth embodiments and their modifications, the coercive force of the magnetization free layer in each MTJ element needs to be changed by a voltage. Therefore, it is undesirable that the nonmagnetic insulating layer 22 of each MTJ element has a very low resistance area product (RA). A preferable RA is several ten Ω² to several thousand KΩμm². In this case, if the resistance is several thousand KΩμm², the switching in a write operation is mainly caused by a voltage and SOT, and if the resistance is several ten Ωμm², the switching is mainly caused by a voltage, SOT, and STT.

The embodiments of the present invention have been described with reference to the specific examples. However, the present invention is not limited to the specific examples. For example, specific materials, thicknesses, and shapes, of dimensions of the SO layer, and the ferromagnetic material layers, insulating films, antiferromagnetic material layers, nonmagnetic metal layers, and electrodes that serve as the ferromagnetic tunnel junction elements, may be arbitrarily selected by those skilled in the art to carry out the present invention to have similar effects. Such elements and layers are also included in the scope of the present invention.

Similarly, the structure, the material, the shape, and the dimensions of each element included in the magnetic memory according to an embodiment of the present invention may be arbitrarily selected by those skilled in the art to carry out the present invention to have similar effects. Such elements are included in the scope of the present invention.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 

1. A magnetic memory comprising: a first terminal, a second terminal, and a third terminal; a nonmagnetic conductive layer including a first region, a second region, and a third region, the second region being disposed between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, the nonmagnetic conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.
 2. The magnetic memory according to claim 1, wherein the second region of the nonmagnetic conductive layer includes a first layer and a second layer, the first layer being disposed between the magnetoresistive element and the second layer, the first layer including at least one of the alloys and having a thickness of 3 nm or more.
 3. The magnetic memory according to claim 1, wherein the nonmagnetic conductive layer includes at least one of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35).
 4. The magnetic memory according to claim 1, wherein the nonmagnetic conductive layer includes a first layer and a second layer, the first layer being disposed on a side of the magnetoresistive element, the first layer including at least one of the alloys and having a thickness of 3 nm or more.
 5. A magnetic memory comprising: a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal; a nonmagnetic conductive layer including a first region, a second region, a third region, a fourth region, and a fifth region, the second region being disposed between the first region and the fifth region, the third region being disposed between the second region and the fifth region, the fourth region being disposed between the third region and the fifth region, the first region being electrically connected to the first terminal, the fifth region being electrically connected to the second terminal, and the third region being electrically connected to the third terminal; a first magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the fourth terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; and a second magnetoresistive element disposed to correspond to the fourth region, including a third magnetic layer electrically connected to the fifth terminal, a fourth magnetic layer disposed between the third magnetic layer and the fourth region, and a second nonmagnetic layer disposed between the third magnetic layer and the fourth magnetic layer, the nonmagnetic conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.
 6. The magnetic memory according to claim 5, wherein the second region of the nonmagnetic conductive layer includes a first layer and a second layer and the fourth region includes a third layer and a fourth layer, the first layer being disposed between the second magnetic layer and the second layer, the first layer including at least one of the alloys and having a thickness of 3 nm or more, the third layer being disposed between the fourth magnetic layer and the fourth layer, and the third layer including at least one of the alloys and having a thickness of 3 nm or more.
 7. The magnetic memory according to claim 5, wherein the nonmagnetic conductive layer includes at least one of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35).
 8. The magnetic memory according to claim 5, wherein the nonmagnetic conductive layer includes a first layer and a second layer, the first layer being disposed on a side of the first and second magnetoresistive elements, the first layer including at least one of the alloys and having a thickness of 3 nm or more.
 9. A magnetic memory comprising: a first terminal, a second terminal, a third terminal, and a fourth terminal; a nonmagnetic conductive layer including a first region, a second region, a third region, and a fourth region, the second region being disposed between the first region and the fourth region, the third region being disposed between the second region and the fourth region, the first region being electrically connected to the first terminal, and the fourth region being electrically connected to the second terminal; a first magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; and a second magnetoresistive element disposed to correspond to the third region, including a third magnetic layer electrically connected to the fourth terminal, a fourth magnetic layer disposed between the third magnetic layer and the third region, and a second nonmagnetic layer disposed between the third magnetic layer and the fourth magnetic layer, the nonmagnetic conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.
 10. The magnetic memory according to claim 9, wherein the second region of the nonmagnetic conductive layer includes a first layer and a second layer, and the third region includes a third layer and a fourth layer, the first layer being disposed between the second magnetic layer and the second layer, the first layer including at least one of the alloys and having a thickness of 3 nm or more, the third layer being disposed between the fourth magnetic layer and the fourth layer, and the third layer including at least one of the alloys and having a thickness of 3 nm or more.
 11. The magnetic memory according to claim 9, wherein the nonmagnetic conductive layer includes at least one of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35).
 12. The magnetic memory according to claim 9, wherein the nonmagnetic conductive layer includes a first layer and a second layer, the first layer being disposed on a side of the first and second magnetoresistive elements, the first layer including at least one of the alloys and having a thickness of 3 nm or more.
 13. A magnetic memory comprising: a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring; a first terminal, a second terminal electrically connected to the fifth wiring, a third terminal, and a fourth terminal electrically connected to the fifth wiring; a first conductive layer including a first region, a second region, and a third region, the second region being disposed between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a second conductive layer including a fourth region, a fifth region, and a sixth region, the fifth region being disposed between the fourth region and the sixth region, the fourth region being electrically connected to the third terminal, and the sixth region being electrically connected to the fourth terminal; a first magnetoresistive element disposed to correspond to the second region, including a first magnetic layer, a second magnetic layer disposed between the first magnetic layer and the second region, and a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a second magnetoresistive element disposed to correspond to the fifth region, including a third magnetic layer, a fourth magnetic layer disposed between the third magnetic layer and the fifth region, and a second nonmagnetic layer disposed between the third magnetic layer and the fourth magnetic layer; a first transistor including a fifth terminal electrically connected to the first magnetic layer, a six terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; a second transistor including a seventh terminal electrically connected to the first terminal, an eighth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring; a third transistor including a ninth terminal electrically connected to the third magnetic layer, a tenth terminal electrically connected to the third wiring, and a third control terminal electrically connected to the fourth wiring; and a fourth transistor including an eleventh terminal electrically connected to the third terminal, a twelfth terminal electrically connected to the second wiring, and a fourth control terminal electrically connected to the fourth wiring, the first wiring, the second wiring, the third wiring, and the fourth wiring, and the first transistor, the second transistor, the third transistor, and the fourth transistor being disposed in a first level, the first conductive layer and the first magnetoresistive element being disposed in a second level that is above the first level, the fifth wiring being disposed in a third level that is above the second level, and the second conductive layer and the second magnetoresistive element being disposed in a fourth level that is above the third level, and the first conductive layer and the second conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.
 14. The magnetic memory according to claim 13, wherein: the second region of the first conductive layer includes a first layer and a second layer, the first layer being disposed between the second magnetic layer and the second layer, the first layer including at least one of the alloys and having a thickness of 3 nm or more; and the fifth region of the second conductive layer includes a third layer and a fourth layer, the third layer being disposed between the fourth magnetic layer and the fourth layer, the third layer including at least one of the alloys and having a thickness of 3 nm or more.
 15. The magnetic memory according to claim 13, wherein the first magnetoresistive element is disposed above the first conductive layer, and the second magnetoresistive element is disposed above the second conductive layer.
 16. The magnetic memory according to claim 13, wherein the first conductive layer and the second conductive layer include at least one of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35).
 17. The magnetic memory according to claim 13, wherein: the first conductive layer includes a first layer and a second layer, the first layer being disposed on a side of the first magnetoresistive element, the first layer including at least one of the alloys and having a thickness of 3 nm or more, and the second conductive layer includes a third layer and a fourth layer, the third layer being disposed on a side of the second magnetoresistive element, the third layer including at least one of the alloys and having a thickness of 3 nm or more. 